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Magazine Name : Ieee Transactions On Electron Devices
Year : 2004Volume number : 51Issue:02
Large Grain Poly-Si (10 M) Tfts Prepared By Excimer Laser Annealing Through A Thick Sion Absorption Layer(Article) Subject:
Excimer Laser Annealing
Author:
Sheng
Da Liu
page:
166
-
172
A Numerical Study Of Scaling Issues For Schottky-Barrier Carbon Nanotube Transistors(Article) Subject:
Carbon Nanotube Transistors
Author:
Jing
Guo
page:
172
-
177
The Analysis Of Dark Signals In The Cmos Aps Imagers From The Characterization Of Test Structures(Article) Subject:
Cmos Active Pixel Sensor
Author:
Hyuck
Kwon
page:
178
-
184
Noise Analysis Of High-Gain, Low-Noise Column Readout Circuits For Cmos Image Sensor(Article) Subject:
Complementary Metal-Oxide Semicconductor (Cmos) Image Sensor
Author:
Nobuhiro
Kawai
page:
185
-
194
A Global Interconnect Optimization Scheme For Nanometer Scale Vlsi With Implications For Latency, Bandwidth, And Power Dissipation(Article) Subject:
Bandwidth
Author:
Man Lung
Mui
page:
195
-
203
Large Domains Of Continuous Grain Silicon On Glass Substrate For High-Performance Tfts(Article) Subject:
Grain Boundaries
Author:
Toshio
Mizuki
page:
204
-
211
Improved Off-Current And Subthreshold Slope In Aggressively Scaled Poly-Si Tfts With A Single Grain Boundary In The Channel(Article) Subject:
Defect
,
Device Simulation
Author:
Philip M
Walker
page:
212
-
219
The Electrical And Material Characterization Of Hafnium Oxynitride Gate Dielectrics With Tan-Gate Electrode(Article) Subject:
Crystallinity
Author:
Chang Seok
Kang
page:
220
-
227
A Simulation Study Of Gate Iine Edge Roughness Effects On Doping Profiles Of Short-Channel Mosfet Devices(Article) Subject:
Doping Profiles
Author:
Shiying
Xiong
page:
228
-
232
Comparisons Of Conventional, 3-D, Optical, And Rf Interconnects For On-Chip Clock Distribution(Article) Subject:
Clock Distribution
Author:
Kuan-Neng
Chen
page:
233
-
239
Silicon-On-Nothing Mosfets: Performance,Short-Channel Effects, And Backgate Coupling(Article) Subject:
Doping Modulation
Author:
Jeremy
Pretet
page:
240
-
245
A New 2-D Model For The Potential Distribution And Threshold Voltage Of Fully Depleted Short-Channel Si-Sol Mesfets(Article) Subject:
Bottom Potential
Author:
Prashant
Pandey
page:
246
-
254
An Efficient Noise Isolation Technique For Soc Application(Article) Subject:
Integrated Circuits
Author:
Tung-Sheng
Chen
page:
255
-
260
Analytical Drain Thermal Noise Current Model Valid For Deep Submicron Mosfets(Article) Subject:
Carrier Heating
Author:
Kwangseok
Han
page:
261
-
269
Cryogenic Capacitive Transimpedance Amplifier For Astronomical Infrared Detectors(Article) Subject:
Capacitive Transimpedance Amplifier
Author:
H.
Nagata
page:
270
-
278
Vertical Tunnel Field-Effect Transistor(Article) Subject:
Band-To-Band -Tunneling
Author:
Krishna Kumar
Bhuwalka
page:
279
-
295
A Numerical Study Of Scaling Issues For Schottky-Barrier Carbon Nanotube Transistors(Article) Subject:
Carbon Nanotube Transistors
Author:
Jing
Guo
page:
-
-
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